Code Of Divergence5 Citizen's own device 5

citizen's public domain computer

O'ksi'D, cod5.com

3

DRAFT

28 ~ 35

256 ~ 243 -> +/-127 ~ +/-121

Abstact

This paper presents a design of a disruptive ternary computer.


Index Terms

multiple-valued logic (MVL) design, FPGA.

Introduction

Nowadays computer are designed using binary logic, but ternary logic is investigated as an alternative since long time ago in the history of computer science.

Our world is made of approximations. Every human being are nearly the same but not fully the same. In this document we try to find the lesser common features of binary and ternary logic to build an approximation of the best computer system.

Numeral system

Table of power of 2 and 3 with their maximal balanced signed value: 
power  0 1 2  3  4   5   6   7    8      9    10   11   12   13
base2  1 2 4  8 16  32  64  128  256   512  1024 2048 4096 8192
+/-b2  0 0 1  3  7  15  31   63  127   255   511 1023 2047 4095
base3  1 3 9 27 81 243 729 2187 6561 19683 59049
+/-b3  0 1 4 13 40 121 364 1093 3280  9841 29524
A trit is the basic unit of ternary logic, it can take the value of +1, 0 or -1.

Three balanced trits (a tribble) encoding : 
power  2  1  0
base3  9  3  1
-13    -  -  -
-12    -  -  0
-11    -  -  +
-10    -  0  -
 -9    -  0  0
 -8    -  0  +
 -7    -  +  -
 -6    -  +  0
 -5    -  +  +
 -4    0  -  -
 -3    0  -  0
 -2    0  -  +
 -1    0  0  -
  0    0  0  0
  1    0  0  +
  2    0  +  -
  3    0  +  0
  4    0  +  +
  5    +  -  -
  6    +  -  0
  7    +  -  +
  8    +  0  -
  9    +  0  0
 10    +  0  +
 11    +  +  -
 12    +  +  0
 13    +  +  +
UPU

CPU

The CPU has 3 general purpose registers. 
ADD
SUB
SHIFT
CONS
ANY
XOR
LD
ST
JMP
BEQZ
BNEZ
BLTZ
BGTZ
BLEZ
BGEZ

Instruction set details

Pseudocode operation description is in C89 language.
A is the accumulator.
PC is the program counter.
bus is the source of data.

ADD - ADD

trit  04       03      02      01       00 
     ----------------------------------------
    |     ADD       |     mode      |  bus   |
     ----------------------------------------

Format:

ADD A, A, bus

Description:

The contents of register Rsrc and the contents of general register Rval or the immediate value are added to form a result.
The result is placed into register Rdest.

Operation:

T:


Binary Coded Ternary

We encode a single trit as two bits in binary. 
- = 10
0 = 00
+ = 01

MSCII - Morse Standard Code for Information Interchange


long  = -  (10)
short = +  (01)
pause = 0  (00)

-.-.--	'!'
.-..-.	'"'
...-..-	'$'
.--.-	'%'
.-...	'&'
.----.	'''
-.--.	'('
-.--.-	')'
--..-	'*'
.-.-.	'+'
--..--	','
-....-	'-'
.-.-.-	'.'
-..-.	'/'
-----	'0'
.----	'1'
..---	'2'
...--	'3'
....-	'4'
.....	'5'
-....	'6'
--...	'7'
---..	'8'
----.	'9'
---...	':'
-.-.-.	';'
----	'<'
-...-	'='
---.	'>'
..--..	'?'
.--.-.	'@'
.-.-	'['
...-.	'\'
.-..-	']'
......	'^'
..--.-	'_'
.-      'a'
-...	'b'
-.-.	'c'
-..     'd'
.       'e'
..-.	'f'
--.     'g'
....	'h'
..      'i'
.---	'j'
-.-     'k'
.-..	'l'
--      'm'
-.      'n'
---     'o'
.--.	'p'
--.-	'q'
.-.     'r'
...     's'
-       't'
..-     'u'
...-	'v'
.--     'w'
-..-	'x'
-.--	'y'
--..	'z'
..--	'{'
...-..	'|'
..--.	'}'
.......	'~'

Conclusion

This paper presented the design of a "new" computer.

References

public domain public domain MMXXI August 8 - MMXXIV March 20 by JML